Wafer scale aligned sub-25nm metal nanowires on Silicon (110) using PEDAL lift-off process

We have demonstrated a new PEDAL process to make sub-25 nm nanowires template across the entire Silicon (110) wafer suitable for wafer-scale nanoimprinting. The “PEDAL lift-off” has the ability to fabricate metal nanowires directly on the wafers without using nanoimprint techniques. The process involves defining the edge by etching a trench, patterned using conventional i-line lithography, and followed by deposition of alternating layers of silicon nitride and a-silicon. The thickness of these layers determines the width and spacing of the nanowires. Later this stack is planarized to the top surface of the trench by spinning polymer and then dry etching the polymer, nitride and a-silicon stack with non-selective RIE etch recipe. Selective wet etch of either nitride or a-silicon gives us the template of array of aligned nanowires. The desired metal is evaporated by e-beam on the template and metal deposited on a-silicon layer is lifted-off by wet-etching a-silicon layer. This gives us the metal nanowires deposited on the insulating silicon nitride layer across the wafer. The process has the flexibility of routing the nanowires around the Logic and memory modules across the entire wafer. The fabrication facilities required for the process are readily available and this process provides the great alternative to existing slow and/or costly nanowire patterning techniques. PEDAL lift-off process when incorporated with Atomic Layer Deposition has the ability to make wafer-scale aligned sub-5 nm wide nanowires.